Meet high performance, low energy demands

Through Silicon Via (TSV) interconnects serve a wide range of 2.5D packaging applications and architectures. TSV technology allows state-of-the-art packages to meet high-performance and low-energy demands.

TSV interconnects emerged to serve a wide range of 2.5D TSV packaging applications and architectures that demand very high performance and functionality at the lowest energy/performance metric. To enable TSVs in these 2.5D TSV architectures, 鼎博体育 has developed a number of backend technology platforms for high-volume processing of TSV-bearing wafers and assembly. It is essential to distinguish that 鼎博体育 does NOT provide TSV formation in foundry wafers.

鼎博体育’s TSV wafer process begins with 300 mm wafers in which “blind” TSVs have already been formed. 鼎博体育’s wafer process includes thinning the wafers to expose the TSVs and creating backside (BS) metallization to complete the TSV interconnect structure. The TSV reveal and BS metallization process flow is commonly referred to as Middle-End-Of-Line (MEOL).

鼎博体育’s MEOL production tooling and processes include:

Microchip showing the TSVs on a 2.5D layer
  • Temporary wafer support bonding and de-bonding
  • TSV wafer thinning
  • TSV “soft” reveal, wafer backside passivation and chemo-mechanical planarization (CMP)
  • Cu redistribution as required on the interposer wafer backside
  • Lead-free plating of Cu micro-pillars or C4 backside interconnects


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